FIELD OF THE INVENTION
The present invention relates to interrupt systems for computers and, more particularly, to interrupt systems for computers using multiple processors.
There is a continual demand by users of computers for improved computers having greater capabilities at an acceptable cost. In the past, this demand has been primarily met by increasing the performance rapidity of the computer data manipulations and by increasing the size of the data portions being manipulated, both improvements made using primarily a single central data processing unit. As this manner of improving computer capabilities has progressed, the various electronic means of implementing these improvements have begun to approach certain physical limitations making further gains more difficult to achieve and more costly.
One way in getting around these difficulties is to use more than one central processor. Thus, a sequence of computer manipulations forming a process can be divided in one or more of various ways to permit allocating various portions of the computer manipulations to each of such additional central processors. Since these processors can be operated simultaneously, there is the possibility of getting more of the manipulations, which would have been sequentially done by a single processor, to be completed simultaneously by the several processors to thereby enable more manipulations being completed per unit of time.
This manner of achieving computer capability improvements is not free from problems, however. Even though the manipulation tasks are divided in some manner and assigned to the various central processors, the processors usually cannot operate independently but may depend on results obtained from one or more of the other processors, or on access to the same data in a common memory at the same time as does one or more of the other procesors, or the like. To accommodate such needs, an interrupt arrangement is required permitting a processor to interrupt another to obtain results therefrom, for example, or to be given access to the memory portion also required by the other processor, or for some other purpose. Further, many pieces of equipment connected to the computer will have occasion to interrupt one or more processors for purposes related to that piece of equipment or to provide some input related to other activities undertaken by the computer.
Such an interrupt arrangement can be implemented by having an interrupt notice system to provide a notification signal to any of the processors, in a cooperative arrangement thereof, that some other processor in the arrangement has begun steps to interrupt its operation. The computer must have some further arrangements in place so that, upon receipt of such an interrupt notice, the processors involved can interact in a manner to find a way to satisfy the needs of each to permit operations after some point to continue for each.
An interrupt notice system could be operated on the basis of each processor being directly interconnected to each other processor through a central controller in a cooperative arrangement. Each processor would have the ability to send signals to every other processor on the basis of an address of that other processor in the system. That is, the interrupt notice system controller would have to extend therefrom N signal address lines to each processor in the system where N must be such that 2.sup.N equals or exceeds the number of processors in the system. Further, since each of the processors must be able to initiate an interrupt to be sent to another, there would also have to be N signal lines coming from each processor to the interrupt system controller. In a computer with a small number of processors, this arrangement may be satisfactory but becomes it a burdensome interconnection problem as the number of processors increases significantly.
Thus, for 4 processors, two signal lines in and two signal lines out for each of the four processors are needed leading to 16 total interconnections--just four lines between the interrupt system controller and each of the processors. For 48 processors, however, there will be six lines required to and six lines from each processor giving a total of 288 interconnections for signals coming into the interrupt system controller and 288 interconnections for signals going out from the interrupt system controller. Thus, an interrupt notice system for a multiple procesing arrangement which reduces the numbers of interconnections needed, even though a relatively large number of processors are used in the computer arrangement, e.g. system, would be desirable.